Mentor Graphics ModelSim SE-64 2019.2


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Mentor Graphics ModelSim SE-64 2019.2

File Size: 864 MiB

Mentor, a Siemens business, is pleased to announce the availability of ModelSim 2019.2, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment.

Index to Release Notes
General Defects Repaired in 2019.2
- QSIM-54154 - (results) Messages printed from VPI or PLI containing the strings "error" or "warning" were counted as tool error and warning and reported in stats output.
User Interface Defects Repaired in 2019.2
- QSIM-18738 - (results) Fixes corner cases that were causing the Colorize system in the Transcript window to malfunction for some customers. Using a color of 0 (Normal) now works as a Start Tag. Also, having an End Tag on another line from its matching Start Tag now correctly cleans up the color escape sequence.
- QSIM-53899 - The font size in the Source window is incorrect under some newer X server configurations. This problem has been resolved.
SystemVerilog Defects Repaired in 2019.2
- [nodvtid] - In some cases, vsim did not generate an error during elaboration when a non-existent class field was the first name in a dotted name.
- QSIM-54192 - A "force -deposit" or $deposit on a net connected to tran primitives failed to take on the forced value.
- QSIM-36267 - Vsim would sometimes leak memory when SystemVerilog strings were used in constant functions defined in a package.
- QSIM-53856 - Use of the 'inside' operator with an array of 'real' type on the RHS (e.g. "myvar inside { array_of_real }") would trigger an internal error "==? operator invalid for REAL". This issue has been fixed.
VHDL Defects Repaired in 2019.2
- QSIM-54334 - References within an uninstantiated package to a locally-defined package instantiation could result in incorrect simulator error messages due to incorrect code generation.
- QSIM-54962 - An object declaration with an initial value (or default value, for signal) that was the parenthesized OPEN reserved word was accepted and resulted in bad code that would crash the simulator. This is a syntax error that is now detected.
- QSIM-54941 - The presence of a package instantiation declaration within the declarative region of a design unit could cause the compiler to incorrectly identify the instantiation as a standalone design unit when compiling a source file with a -just command-line switch. As a consequence, it is possible the extracted generic map clause of the instantiation will refer to objects that are not in scope, or the containing design unit will be broken into two parts that cannot be compiled without syntax errors.
- QSIM-50634 - (results) In certain cases, optimization of clocked processes with reset was leading to incorrect results. This bug has been fixed.
- QSIM-55460 - A VHDL 2008 IF-GENERATE with ELSIF-GENERATE alternative block(s) could cause a simulator crash if vopt could determine that a condition was FALSE.
- QSIM-55137 - (results) In certain cases, vopt was crashing during optimization of clocked processes. This bug has been fixed.
- QSIM-55531 - If a component or an entity contains a generic whose type is dependent on another generic of the component or entity. Code generation in vcom or vopt could fail.
- QSIM-56373 - A VHDL design unit whose source text is in 2 or more files is not supported. An error will be issued if such a situation is detected.
SystemC Defects Repaired in 2019.2
- QSIM-39643 - Fixed an incorrect flag setting for the pointer types that would cause an sccom (sccom-6165) merge error.
Mixed Language Defects Repaired in 2019.2
- QSIM-53578 - When a write-protected library contained a Verilog DU made visible (as its equivalent ENTITY) by VHDL "use lib.all" in a VHDL design unit, if the VHDL design unit then contained an identifier that was the same as the name of this Verilog module, an error would occur as the equivalent ENTITY was being made. This error happened on Windows platforms only.
SystemVerilog Enhancements in 2019.2
- QSIM-53134 - Added a SystemVerilog Constraint Solver extension. This extension is to enable the seeding of different module instances differently based on their hierarchical path names. The extension is off by default and can be enabled with vsim -svrandext=pathseed.



Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused.

In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim's award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.

The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

Product: Mentor Graphics ModelSim
Version: SE 2019.2
Supported Architectures: x64
Language: English
System Requirements: PC *
Supported Operating Systems: *
Size: 864 MiB

System Requirements:
Starting 2019.1 release, support for Windows 7 and 8.1 have discontinued. Only Windows 10 is supported. However, we continue to support Windows 7 & 8.1 with our 10.6 and 10.7 release series until their planned End Of Life (10.6 EOL - mid 2019, 10.7 EOL - mid 2020) to coincide with Microsoft's EOL for Windows 7.

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